Circuits with improved power supply rejection

ABSTRACT

Circuit comprising a noise suppressing circuitry ( 40 ) having an input ( 42 ) for a first voltage (VDD) and an output ( 43 ) for providing a supply voltage (VDDfiltered). The circuit further comprises a MOSFET-based switch ( 41 ) with a MOSFET (MP) being situated in a well, whereby a supply voltage (VDDfiltered) is applied to the well ( 67 ). The first voltage (VDD) is a global voltage used elsewhere in the same circuit, and the supply voltage (VDDfiltered) is less-noisy than the first voltage (VDD).

The present invention relates to circuits having an improved powersupply rejection.

In particular, the present invention relates to analog circuits ormixed-signal circuits.

With ever increasing integration level and the advanced processtechnology, analog chips and mixed-signal chips now contain more andmore circuit blocks. As a consequence, the power supply of a chip isbecoming increasingly hostile to sensitive analog and mixed-signalcircuits.

The big challenge to designers is to maintain or improve the circuitperformance on one hand and to reduce the supply voltage on the otherhand. This entails circuits with higher power supply rejection (PSR).

Analog switches are important and indispensable elements in circuitriessuch as sampling circuits, switched-capacitor (SC) circuits,switched-current (SI) circuits, automatic gain control (AGC), circuitsfor testing purpose, and so forth.

Power-supply errors occur when noise from the power supply mixes withthe signals being processed by the respective circuit. The power supplyrejection specification is a measure of how well a circuit is able toblock power supply noise. In other words, PSR is the ability of acircuit to be unaffected by power supply noise and variations. Dependingon the kind of circuit implementation, values of 100 dB or more arecommon. PSR varies with frequency. If the PSR is divided by the circuitgain (hence input-referred), the term becomes PSRR, or power-supplyrejection ratio.

An automatic gain control (AGC) circuit is quite a complex circuitprimarily used in communication systems to achieve the highestsensitivity and to cope with the huge range of signal strengths. FIG. 1shows a schematic block diagram of a receiver 10 designed for employmentin a communication system. Here, signals undergo two AGCs 11 and 12before being processed by base-band (BB) circuitries 13. Basically, anAGC provides several gains in steps within a certain range. FIG. 2Aillustrates the principle of an AGC 11. With the switches S1 opened, thegain of the AGC circuit 11 is given by the ratio of the resistors R3/R1.When the switches S1 are closed, the resistors R1 and R2 will be inparallel, yielding a higher gain of (1+R1/R2)(R3/R1). The change in gainis 1+R1/R2. More gains/steps are available when more switches andresistors are added.

The switches (S1) 20 in FIG. 2A are normally built with complementarymetal-oxide semiconductor field-effect transistors (CMOSFETs) in amanner of the so-called transmission gate, detailed in FIG. 2B. Here, apMOS transistor MP and an nMOS transistor MN are connected in parallel,with two junctions A and B as terminals of the switch 20. A controlsignal (Control) is applied to the gate 21 of the transistor MN and theinverted signal ({overscore (Control)}) to the gate 22 of the transistorMP. The inverted signal ({overscore (Control)}) is provided by aninverter 23.

When using a standard CMOS process, a pMOS transistor is situated in ann-well or on a bulk substrate, and in common practice, this n-well orbulk is required to have the highest potential of the whole circuit,i.e., the power supply VDD, as shown in FIG. 2B where the bulk 25 of thetransistor MP, as well as the power supply line 24 of the inverter 23,are connected to VDD, which is normally global.

Problems arise in conventional circuits because of the fact that theactual power supply that is applied to each circuit is no more a DCvoltage determined by a battery, rather, it becomes very noisy andseverely polluted. If at the output 14 of the AGC 11, for example, thenoise due to inadequate PSR is bigger than the signal received at theantenna 15, the circuit 10 would fail to work properly. This is highlylikely because the signal picked up by the antenna 15 is very weak andthe gain of the LNA 16 and the mixer 17 is limited to 20 to 30 dB.Simulations for the circuit 10 have been made. The simulated result isdepicted in FIG. 6, where curve 51 represents the case where the supplyvoltage VDD is applied to the circuit's bulk, i.e., bulk=VDD.

Like other circuits, the AGC 11 here employs one (or more) operationalamplifiers 18 (op-amps), passive elements such as resistors (orcapacitors), and some analog switches. Depending on theirimplementation, the presence of each part of a circuit has been found todegrade the PSR of the entire circuit. While the op-amp with singleoutput is the dominant source due to its limited PSR, it has been foundout that its PSR can be very high if its output 19 is made differential,as well, like the case in FIG. 2A. Some resistor types, notably n-well,may be more prone to supply variations than other types, say, activetypes. But if poly-resistors are used, they can be consideredvoltage-independent.

Indeed, the PSR of many conventional circuits is very poor andinadequate.

It is an object of the present invention to provide circuits with animproved performance, and devices based on such circuits

It is another object of the present invention to provide circuits anddevices based thereon with an improved PSR.

These and other objects are accomplished by a circuit according to claim1 and an automatic gain control (AGC), according to claim 10, comprisingsuch a circuit.

A circuit comprises, in accordance with the present invention, a noisesuppressing circuitry that has an input for a first voltage and anoutput for providing a supply voltage (VDDfiltered). The circuit furthercomprises a MOSFET-based switch with a MOSFET (MP) being situated in awell. A supply voltage is applied to well, whereby the first voltage isa global voltage used elsewhere in the same circuit and the supplyvoltage is less noisy than the first voltage (VDD). The noisesuppressing circuitry has a noise suppression characteristic wherefrequencies within a bandwidth range around the upper edge of thecircuit's frequency band are damped.

Further advantageous implementations are claimed in claims 2–9.

For a more complete description of the present invention and for furtherobjects and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a schematic representation of a conventional receiver circuitdesigned for employment in a communication system;

FIG. 2A is a schematic representation of an AGC with switchableresistors;

FIG. 2B is a general realization of a transmission-gate switch usingCMOS-FETs;

FIG. 3 is a schematic representation of a transmission-gate switch,according to the present invention;

FIG. 4 is a schematic representation of a transistor whose bulk isconnected to an ideal supply voltage;

FIG. 5A is a schematic representation of another transmission-gateswitch, according to the present invention;

FIG. 5B is a schematic representation of a low-pass filter, according tothe present invention;

FIG. 6 is a schematic diagram demonstrating the effectiveness of theinventive approach;

FIG. 7A is a schematic representation of a transistor with conventionalpower supply;

FIG. 7B is a schematic representation of a transistor; according to thepresent invention;

FIG. 7C is a schematic representation of another transistor; accordingto the present invention;

According to the present invention, an improved performance can beachieved, when the power supply rejection (PSR) of each circuit is highenough. This is possible by connecting the bulk of the transistor MP ina switch 30 to an ideal supply voltage that is a clean and noise-free DCvoltage (VDDideal) of the same value as VDD, as schematicallyillustrated in FIG. 3. The corresponding result (where bulk=VDDideal) isdepicted in FIG. 5 by the reference number 52.

With the present invention, the PSR of the AGC 11, for example, can beimproved by up to 25 dB.

One possible way to provide such a DC voltage is to add a dedicatedcontact pad on the chip to apply an external DC voltage that is cleanand noise-free. This approach, however, is not convenient in chips wherethere is no room on the chip for such an additional contact pad, orwhere the routing of the various signal and supply lines does not allowanother supply line to be routed from such an additional contact pad tothe circuit where the clean and noise-free DC voltage is needed.

According to a first embodiment of the present invention, an improved DCvoltage (VDDfiltered) is generated that is cleaner than the supplyvoltage VDD. The improved DC voltage is a DC voltage derived directlyfrom the supply voltage VDD. A noise suppression circuitry 40 isemployed to provide the improved DC voltage at an output 43, asschematically illustrated in FIG. 4. In the present example, theimproved DC voltage is applied to the bulk 44 of a transistor MP. Thetransistor MP can be part of a MOSFET-based switch, for example.

A second embodiment is illustrated in FIGS. 5A and 5B. The circuitcomprises a noise suppressing circuitry 40 and a transmission-gateswitch 41. The noise suppressing circuitry 40 has an input 42 for afirst voltage (in the present example VDD) and an output 43 forproviding an improved DC voltage (VDDfiltered). The transmission-gateswitch 41 is a MOSFET-based switch with an N-MOS FET (MN) and a P-MOSFET (MP) being situated in a bulk or n-well. The improved DC voltage(VDDfiltered) is applied to the bulk 44 in which the P-MOS FET (MP) issituated. The first voltage (VDD) is an internal voltage, i.e., avoltage that is used elsewhere in the same chip. The improved DC voltage(VDDfiltered) is less-noisy than the first voltage, and the noisesuppressing circuitry 40 has a noise suppression characteristic wherefrequencies within a wide bandwidth of interest (herein referred to asbandwidth range) around the upper edge of the circuit's frequency bandare damped. In the present example, a low-pass filter (LPF) serves asnoise suppressing circuitry 40. The LPF is employed to provide theimproved DC voltage (VDDfiltered). A 1st-order LPF is already adequateto achieve remarkable results.

The LPF may take the supply voltage VDD as an input signal and generatesa cleaner and less-noisy output voltage, herein referred to asVDDfiltered. By adjusting the corner frequency of the LPF, almost thesame performance can be obtained as with the voltage VDDideal(represented by curve 52 in FIG. 6).

As mentioned above, a simple 1st-order LPF will be sufficient. There arevarious ways to realize a 1st-order LPF. Note that when using a LPF, thePSR improvement only takes place for frequencies outside the bandwidthof the LPF. For many applications a larger RC time constant, i.e., lowercorner frequency, is called for. For this reason, the realization of avery large time constant using a passive resistor and capacitor wouldlead to a relative big area overhead.

According to the second embodiment of the present invention, the LPF 40has a very large time constant. The LPF 40 comprises simulatedresistors. In FIG. 5B, at the place of a passive resistor two pMOStransistors MP0 and MP1, as well as a current source Ib are put. Thetransistor MP1 is biased in the sub-threshold region by the transistorMP0 and the current source Ib. Detailed simulations revealed that with asupply voltage VDD=2.6V, a current Ib=1 μA, an MP0 transistor of size1/21, a 1.5 GΩ resistor is obtained with an MP1 transistor of a size0.5/3. In that simulation, the value of the capacitor C is 0.75 pF. Thecalculation of the time constant should include the parasiticcapacitances of the n-well. With these circuit elements, the reached PSR(bulk=VDDfiltered) is depicted by reference number 53 in FIG. 6. Fromthe curve 53 in FIG. 6 it can be derived that in the present example theinventive PSR method is effective from the upper edge frequency of about2.5 MHz down to as low as about 1 kHz, and up to about 7–8 MHz. Thecorner frequency of the LPF 40 can be shifted to lower frequencies byincreasing the time constant, thus approaching the performance obtainedwith VDDideal (see curve 52 in FIG. 6).

The conditioning of the power supply voltage is achieved using a noisesuppression circuitry. This noise suppression circuitry produces a veryprecise and stable voltage over a range of temperature and power supplyconditions, whereby it takes an internal voltage as an input voltagefrom which it produces an output voltage that is cleaner than theinternal voltage.

When referring to an internal voltage, a voltage is meant that isalready available on the chip. In connection with the present invention,VDD is usually used as internal voltage. VDD stems from one or more VDDpins of the circuit and its lines go to almost everywhere within thechip. Hence, it is highly likely to find such a VDD line in the vicinityof the switches where an improved DC voltage (VDDfiltered) needs to begenerated and applied to the bulk.

As mentioned in the above, the bulk 61 of pMOS transistor 60 (MP) in aswitch is in conventional circuits connected to the global supply VDD,as illustrated in FIG. 7A. This differs itself strongly from theapproach proposed herein and illustrated in FIGS. 3, 5A, 7B, and 7C. InFIG. 7B, the n-well 63 of a transistor 62 (MP) is connected to anothernode 64 rather than VDD 65, and this node 64 is by no meansshort-circuited with VDD 65.

According to FIG. 7C, the bulk 67 of a pMOS transistor 66 (MP) in aswitch is connected to the output 68 of a low-pass filter 69. The input70 of the LPF 69 is connected to VDD.

Any other type of low-pass filter can be used in connection with thepresent invention. Instead of a low-pass filter a band-pass filter canbe employed, or a voltage regulator may serve as noise suppressingcircuitry. When using a voltage regulator, the improved DC voltage(VDDfiltered) is smaller than VDD.

The present invention is very well suited for use in analog circuits ormixed-signal circuits. The invention can be employed in systems on achip, in audio amplifiers (e.g., for cellular phones), in chips for PDAapplications and in chips for any other portable electronic device. Theinvention is well suited for use in sampling circuits,switched-capacitor (SC) circuits, switched-current (SI) circuits,automatic gain control (AGC), and circuits for testing purposes, just togive some examples.

At lower frequencies (e.g., below A=2 MHz in FIG. 6), the power supplyrejection is not a serious problem. The noise suppression circuitryproposed herein thus preferably is designed such that it shows an effectat about A=2 MHz.

It is an advantage of the various embodiments presented herein that theyfeature an improved Power Supply Rejection Ratio (PSRR). According tothe present invention, the PSRR performance can be improved for manyapplications by up to 25 dB over known solutions, by reducing the effectof noise on the power supply. In other words, up to a 10-foldimprovement can be achieved.

It is another advantage of the present invention that it allows systemdesigners to save space and to increase the cost-effectiveness.

In the drawings and specification there has been set forth preferredembodiments of the invention and, although specific terms are used, thedescription thus given uses terminology in a generic and descriptivesense only and not for purposes of limitation.

1. Circuit comprising a noise suppressing circuitry (40; 69) having aninput (42; 70) for a first voltage (VDD) and an output (43; 68) forproviding a supply voltage (VDDfiltered), a MOSFET-based switch (41)with a MOSFET (MP) being situated in a well (67), where a supply voltage(VDDfiltered) can be applied to well (67), whereby the first voltage(VDD) is a global voltage used elsewhere in the same circuit, the supplyvoltage (VDDfiltered) is less-noisy than the first voltage (VDD), andthe noise suppressing circuitry (40; 69) has a noise suppressioncharacteristic where frequencies within a bandwidth range around theupper edge of the circuit's frequency band are damped.
 2. The circuit ofclaim 1, whereby the MOSFET is a P-MOSFET (MP) and the well is an n-well(67).
 3. The circuit of claim 1, whereby the noise suppressing circuitryis a filter (40; 69), preferably a low-pass filter or a band-passfilter.
 4. The circuit of claim 1, whereby the noise suppressingcircuitry is a voltage regulator and the supply voltage (VDDfiltered) issmaller than the first voltage (VDD).
 5. The circuit of claim 3, wherebythe filter (40; 69) is a 1st-order filter.
 6. The circuit of claim 5,whereby the filter (40) comprises pMOS transistors (MP0, MP1), a currentsource (Ib) and at least one capacitor (C).
 7. The circuit of claim 3,whereby the filter (40) comprises simulated resistors, preferablyresistors being simulated by two PMOS transistors (MP0, MP1).
 8. Thecircuit of claim 1, whereby the n-well (67) has the highest potential ofthe whole circuit.
 9. The circuit of claim 1 being an analog circuit ora mixed-signal circuit.
 10. Automatic gain control (AGC) comprising acircuit according to claim 1.